11/28/2023 0 Comments 486 cpu transistor sizeThe 300 MHz version, however, only became available in large quantities later in 1997. The original Klamath Pentium II microprocessor (Intel product code 80522) ran at 233, 266, and 300 MHz and was produced in a 0.35 μm process. The '82459AD' revision of the chip on some 333 MHz and all 350 MHz and faster Pentium IIs lifted this restriction and also offered a full 4 GB cacheable area. Presumably, Intel put this limitation deliberately in place to distinguish the Pentium II from the more upmarket Pentium Pro line, which has a full 4 GB cacheable area. While this limit was practically irrelevant for the average home user at the time, it was a concern for some workstation or server users. Īll Klamath and some early Deschutes Pentium IIs use a combined L2 cache controller / tag RAM chip that only allows for 512 MB to be cached while more RAM could be installed in theory, this would result in very slow performance. General processor performance was increased while costs were cut. The slower and cheaper L2 cache's performance penalty was mitigated by the doubled L1 cache and architectural improvements for legacy code. The improved 16-bit performance and MMX support made it a better choice for consumer-level operating systems, such as Windows 9x, and multimedia applications. It was cheaper to manufacture because of the separate, slower L2 cache memory. The Pentium II was basically a more consumer-oriented version of the Pentium Pro. The Pentium II was also the first P6-based CPU to implement the Intel MMX integer SIMD instruction set which had already been introduced on the Pentium MMX. 2 on the Pentium Pro) these can also be used by either pipeline, instead of each one being fixed to one pipeline. To compensate for the slower L2 cache, the Pentium II featured 32 KB of L1 cache, double that of the Pentium Pro, as well as 4 write buffers (vs. The issues with partial registers was also addressed by adding an internal flag to skip pipeline flushes whenever possible. Most consumer software of the day was still using at least some 16-bit code, because of a variety of factors. Intel improved 16-bit code execution performance on the Pentium II, an area in which the Pentium Pro was at a notable handicap, by adding segment register caches. Off-package cache solved the Pentium Pro's low yield issues, allowing Intel to introduce the Pentium II at a mainstream price level. However, its associativity was increased to 16-way (compared to 4-way on the Pentium Pro) and its size was always 512 KB, twice of the smallest option of 256 KB on the Pentium Pro. The L2 cache ran at half the processor's clock frequency, unlike the Pentium Pro, whose off die L2 cache ran at the same frequency as the processor. This larger package was a compromise allowing Intel to separate the secondary cache from the processor while still keeping it on a closely coupled back-side bus. A fixed or removable heatsink was carried on one side, sometimes using its own fan. The processor and associated components were carried on a daughterboard similar to a typical expansion board within a plastic cartridge. Unlike previous Pentium and Pentium Pro processors, the Pentium II CPU was packaged in a slot-based module rather than a CPU socket. The Pentium II microprocessor was largely based upon the microarchitecture of its predecessor, the Pentium Pro, but with some significant improvements. However, the older family would continue to be produced until June 2001 for desktop units, September 2001 for mobile units, and the end of 2003 for embedded devices. In February 1999, the Pentium II was replaced by the nearly identical Pentium III, which only added the then-new SSE instruction set. The Xeon was characterized by a range of full-speed L2 cache (from 512 KB to 2048 KB), a 100 MT/s FSB, a different physical interface ( Slot 2), and support for symmetric multiprocessing. The Celeron was characterized by a reduced or omitted (in some cases present but disabled) on-die full-speed L2 cache and a 66 MT/s FSB. In 1998, Intel stratified the Pentium II family by releasing the Pentium II-based Celeron line of processors for low-end workstations and the Pentium II Xeon line for servers and high-end workstations. However, its L2 cache subsystem was a downgrade when compared to the Pentium Pros. Containing 7.5 million transistors (27.4 million in the case of the mobile Dixon with 256 KB L2 cache), the Pentium II featured an improved version of the first P6-generation core of the Pentium Pro, which contained 5.5 million transistors. The Pentium II brand refers to Intel's sixth-generation microarchitecture (" P6") and x86-compatible microprocessors introduced on May 7, 1997. Pentium II processor with MMX technology, SECC cartridge.
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